| Description |
1 online resource. |
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text file |
| Series |
Electronics and telecommunications research
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Electronics and telecommunications research.
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| Bibliography |
Includes bibliographical references and index. |
| Contents |
Preface; Chapter 1; Introduction to Binary Decision Diagrams; 1.1. Boolean Functions; 1.2. Boolean Circuits; 1.3. Boolean Formulae; 1.4. Shannon Trees; 1.5. Definition of BDD; 1.6. Operations on BDD; 1.7. Variable Ordering; 1.8. Applications; 1.9. Results of Numerical Experiments; References; Chapter 2; Boolean Algebras and Boolean Functions; 2.1. Sets; 2.1.1. Methods for Describing Sets; 2.1.2. Sets and Sequences; 2.1.3. Inclusion, Equality, Power, Empty Set; 2.1.4. Operation with Sets; 2.1.5. Partitions, Relations and Functions; 2.2. Definition of Boolean Algebra |
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2.3. Examples of Boolean Algebras2.3.1. Algebra of Subsets of a Given Set; 2.3.2. Arithmetic Boolean Algebra; 2.3.3. Two-Element Boolean Algebra; 2.3.4. Stone's Theorem; 2.4. Inclusion Relation; 2.4.1. Intervals; 2.5. Some Useful Properties; 2.6. Formulae and Functions; 2.6.1. Boolean Formulae; 2.6.2. Boolean Functions; 2.7. Shannon's Expansion; 2.8. Canonical Forms; 2.9. Incompletely Specified Boolean Functions; 2.10. Boolean Algebras of Boolean Functions; References; Chapter 3; BDD: Data Structure and Algorithms for Operation with Boolean Functions; 3.1. Introduction; 3.1.1. Designations |
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3.2. Representation3.3. Properties; 3.3.1. Examples of Functions; 3.3.3. Significantly Complex Functions; 3.4. Operations; 3.4.1. Data Structures; 3.4.2. Reduction; 3.4.3. Execution of Binary Operation (Apply); 3.4.4. Restriction; 3.4.5. Composition; 3.4.6. Satisfy Procedure; References; Chapter 4; BDD Efficient Implementation; 4.1. The Main Ideas; 4.1.1. Shared BDD; 4.1.2. Unique Table and Strong Canonical Form; 4.1.3. ITE Algorithm and Calculated Table; 4.1.4. Complemented Edges; References; Chapter 5; Series-Parallel BDD: Theory and Applications; 5.1. Introduction |
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5.2. Definitions and Basic Properties5.3. Basic Operations; 5.3.1. Reordering; 5.3.2. Merging; 5.3.3. Decomposition; 5.3.4. Extraction; 5.4. SP-BDD and CMOS Circuits; 5.4.1. SP-Restriction; 5.4.2. Minimization of Enclosed SP-BDD; 5.5. SP-BDD Applications; 5.5.1. CMOS Circuit Resynthesis; 5.5.2. Worst-Case Elmore Delay for Transistor SP-Network; Conclusion; References; Chapter 6; Simple Logic Implications (SLI) and False-Noise Analysis; 6.1. Introduction; 6.2. Computing Logic Implications; 6.2.1. Generation of SLIs for Simple Gates; 6.2.2. Generating SLIs for Complex Gates |
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6.2.3. Propagation of SLIs6.2.4. Generation of SLIs with Tristate Gates; 6.3. False Noise Analysis Using SLIs; 6.3.1. Forming the Constraint Graph; 6.3.2. Solving MWIS Problem; 6.4. Extension to Timed SLIs; 6.4.1. Basic Definitions; 6.4.2. Propagation of Timed SLIs; 6.4.3. Using Timed SLIs for False Noise Analysis; 6.5. Implementation and Experimental Results; Conclusion; References; Chapter 7; Detecting False Paths in Static Timing Analysis Based on Logic Implications; 7.1. Introduction; 7.2. Static Timing Analysis; 7.3. Forming Logic Constraints |
| Local Note |
eBooks on EBSCOhost EBSCO eBook Subscription Academic Collection - North America |
| Subject |
Digital electronics.
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Digital electronics. |
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Binary system (Mathematics)
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Binary system (Mathematics) |
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Algebra, Boolean.
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Algebra, Boolean. |
| Genre/Form |
Electronic books.
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| Added Author |
Glebov, Alexei L., editor.
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| Other Form: |
Print version: Logic of digital circuits Hauppauge, New York : Nova Science Publishers, Inc., [2016] 9781634842488 (DLC) 2016017074 |
| ISBN |
9781634852395 (electronic book) |
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1634852397 (electronic book) |
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9781634842488 (softcover) |
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1634842480 (hardcover) |
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