LEADER 00000cam a2200673Mu 4500 
001    on1223089197 
003    OCoLC 
005    20211008041809.0 
006    m     o  d         
007    cr cnu---unuuu 
008    201121s2020    xx      o     ||| 0 eng d 
019    1184679172 
020    1839530324 
020    9781839530326|q(electronic book) 
020    |z1839530316 
020    |z9781839530319 
035    (OCoLC)1223089197|z(OCoLC)1184679172 
040    EBLCP|beng|cEBLCP|dYDX|dUKAHL|dN$T|dOCLCF|dOCLCO 
049    RIDW 
050  4 QA268 
082 04 621.395 
090    QA268 
100 1  Sengupta, Anirban|c(Computer scientist)|0https://
       id.loc.gov/authorities/names/no2020034427 
245 10 Frontiers in Securing IP Cores :|bForensic Detective 
       Control and Obfuscation Techniques. 
264  1 Stevenage :|bInstitution of Engineering & Technology,
       |c2020. 
300    1 online resource (365 pages). 
336    text|btxt|2rdacontent 
337    computer|bc|2rdamedia 
338    online resource|bcr|2rdacarrier 
340    |gpolychrome|2rdacc 
347    text file|2rdaft 
490 1  Materials, Circuits and Devices Ser. 
500    Description based upon print version of record. 
500    5.6 Signature detection in a multi-level watermarked IP 
       core. 
505 0  Intro -- Title -- Copyright -- Contents -- Preface -- 
       Acknowledgements -- About the author -- Foreword of the 
       IET book 'Frontiers in Securing IP Cores: Forensic 
       detective control and obfuscation techniques' -- Foreword 
       for IET book 'Frontiers in Securing IP Cores: Forensic 
       detective control and obfuscation techniques' -- List of 
       acronyms -- 1 Introduction to hardware (IP) security: 
       forensic detective control and obfuscation of digital 
       signal processing (DSP) cores -- 1.1 Hardware security: an
       introduction -- 1.2 Hardware security of DSP cores: using 
       high-level synthesis (HLS) framework or ESL 
505 8  1.3 Security: energy trade-off in high-level synthesis for
       hardware security of DSP cores -- 1.4 Design space 
       exploration systems used in HLS: utility in performing 
       energy or area-security trade-offs -- 1.5 Comparative 
       perspective of different security techniques used for DSP 
       cores -- 1.6 Conclusion -- 1.7 Questions and exercises -- 
       References -- 2 Forensic detective control using hardware 
       steganography for IP core protection -- 2.1 Introduction -
       - 2.2 Threat model -- 2.3 Selected contemporary approaches
       -- 2.4 IP core steganography model 
505 8  2.5 Forensic detective control using hardware (IP core) 
       steganography -- 2.6 Design process of a steganography-
       embedded IP core: a case study on 8-point DCT -- 2.7 
       Security features of hardware steganography -- 2.8 
       Analysis of case studies -- 2.9 Conclusion -- 2.10 
       Questions and Exercises -- References -- 3 Forensic 
       detective control using a digital signature-based 
       watermark for IP core protection -- 3.1 Introduction -- 
       3.2 Threat models of an IP core -- 3.3 Selected 
       contemporary approaches -- 3.4 Security modules employed 
       in digital signature-based watermarks 
505 8  3.5 Forensic detective control using a digital signature-
       based watermark -- 3.6 Case study on 8-point DCT used in 
       image compression -- 3.7 Desirable properties of a digital
       signature-based watermark -- 3.8 Threat scenarios and 
       their countermeasures using digital signature-based 
       watermarks -- 3.9 Analysis based on case studies -- 3.10 
       Conclusion -- 3.11 Questions and exercises -- References -
       - 4 Protection of fault-secured IP cores using digital 
       signature-based watermarks -- 4.1 Introduction -- 4.2 
       Threat model -- 4.3 Selected contemporary approaches 
505 8  4.4 Forensic detective control of fault-secured IP cores 
       using digital signature-based watermarks -- 4.5 Case study
       on a fault-secured, finite impulse response (FIR) filter -
       - 4.6 Analysis of case studies -- DSP cores -- 4.7 
       Conclusion -- 4.8 Questions and exercises -- References --
       5 Multi-level watermark for IP protection -- 5.1 
       Introduction -- 5.2 Discussion on selected approaches -- 
       5.3 Salient features and advantages of multi-level 
       watermarks -- 5.4 Embedding signatures as secret marks -- 
       5.5 Design process of a multi-level watermarked IP core 
520    This book presents advanced forensic detective control and
       obfuscation techniques for securing hardware IP cores by 
       exploring beyond conventional technologies. 
590    eBooks on EBSCOhost|bEBSCO eBook Subscription Academic 
       Collection - North America 
650  0 Cryptography.|0https://id.loc.gov/authorities/subjects/
       sh85034453 
650  0 Industrial property.|0https://id.loc.gov/authorities/
       subjects/sh85065922 
650  0 Microprocessors.|0https://id.loc.gov/authorities/subjects/
       sh85084898 
650  0 Signal processing|xDigital techniques.|0https://id.loc.gov
       /authorities/subjects/sh85122398 
650  7 Cryptography.|2fast|0https://id.worldcat.org/fast/884552 
650  7 Industrial property.|2fast|0https://id.worldcat.org/fast/
       971584 
650  7 Microprocessors.|2fast|0https://id.worldcat.org/fast/
       1020008 
650  7 Signal processing|xDigital techniques.|2fast|0https://
       id.worldcat.org/fast/1118285 
655  4 Electronic books. 
776 08 |iPrint version:|aSengupta, Anirban|tFrontiers in Securing
       IP Cores : Forensic Detective Control and Obfuscation 
       Techniques|dStevenage : Institution of Engineering & 
       Technology,c2020|z9781839530319 
830  0 Materials, Circuits and Devices Ser. 
856 40 |uhttps://rider.idm.oclc.org/login?url=https://
       search.ebscohost.com/login.aspx?direct=true&scope=site&
       db=nlebk&AN=2569705|zOnline ebook via EBSCO. Access 
       restricted to current Rider University students, faculty, 
       and staff. 
856 42 |3Instructions for reading/downloading the EBSCO version 
       of this ebook|uhttp://guides.rider.edu/ebooks/ebsco 
901    MARCIVE 20231220 
948    |d20211213|cEBSCO|tEBSCOebooksacademic NEW Oct-Nov 5018
       |lridw 
994    92|bRID