Description |
1 online resource (xl, 364 pages) : illustrations. |
Physical Medium |
polychrome |
Description |
text file |
Series |
IET materials, circuits and devices series ; 76
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Materials, circuits and devices series ; 76.
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Bibliography |
Includes bibliographical references and index. |
Contents |
Introduction : secured and optimized hardware accelerators for DSP and image processing applications / Anirban Sengupta -- Cryptography-driven IP steganography for DSP hardware accelerators / Anirban Sengupta -- Double line of defence to secure JPEG codec hardware for medical imaging systems / Anirban Sengupta -- Integrating multi-key-based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators / Anirban Sengupta -- Multimodal hardware accelerators for image processing filters / Anirban Sengupta -- Fingerprint biometric for securing hardware accelerators / Anirban Sengupta -- Key-triggered hash-chaining-based encoded hardware steganography for securing DSP hardware accelerators / Anirban Sengupta -- Designing a secured N-point DFT hardware accelerator using obfuscation and steganography / Anirban Sengupta and Mahendra Rathor -- Structural transformation-based obfuscation using pseudo-operation mixing for securing data-intensive IP cores / Anirban Sengupta and Mahendra Rathor |
Note |
Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators explored |
Summary |
This book presents state-of-the art security solutions and optimization algorithms employed for designing secured hardware accelerators for DSP, multimedia and image processing applications. Broadly, the theme of this book includes the following: secured and optimized hardware accelerators for DSP and image processing applications; cryptography-driven IP steganography for DSP hardware accelerators; double line of defence to secure JPEG codec hardware for medical imaging systems; integrating multi-key-based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators; multimodal hardware accelerators for image processing filters; fingerprint biometric for securing hardware accelerators; key-triggered hash-chaining-based encoded hardware steganography for securing DSP hardware accelerators; N-point DFT hardware accelerator design using obfuscation and steganography; and structural transformation and obfuscation frameworks for data-intensive IPs. |
Local Note |
eBooks on EBSCOhost EBSCO eBook Subscription Academic Collection - North America |
Subject |
Image processing.
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Image processing. |
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Imaging systems in medicine.
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Imaging systems in medicine. |
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Particle accelerators.
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Particle accelerators. |
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Cryptography.
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Public key cryptography.
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Cryptography. |
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Public key cryptography. |
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image processing. |
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codecs. |
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cryptography. |
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digital signal processing chips. |
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image processing. |
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multimedia computing. |
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steganography. |
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watermarking. |
Indexed Term |
key-triggered hash-chaining-based encoded hardware steganography |
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fingerprint biometric |
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image processing filters |
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multimodal hardware accelerators |
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low-level watermarking |
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multikey-based structural obfuscation |
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medical imaging systems |
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JPEG codec hardware |
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cryptography-driven IP steganography |
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optimized hardware accelerators |
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multimedia hardware accelerators |
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image processing hardware accelerators |
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DSP |
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secured hardware accelerator design |
Genre/Form |
Electronic books.
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Other Form: |
Print version: Sengupta, Anirban Secured Hardware Accelerators for DSP and Image Processing Applications Stevenage : Institution of Engineering & Technology,c2021 9781839533068 |
ISBN |
1839533072 electronic book |
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9781839533075 (electronic book) |
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9781839533068 |
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1839533064 |
Standard No. |
10.1049/PBCS076E |
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