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Author Zjajo, Amir.

Title Real-Time Multi-Chip Neural Network for Cognitive Systems

Imprint Aalborg : River Publishers, 2019.

Item Status

Description 1 online resource (266 pages)
Series River Publishers Series in Circuits and Systems Ser.
River Publishers Series in Circuits and Systems Ser.
Contents Front Cover; Half Title; RIVER PUBLISHERS SERIES IN CIRCUITS AND SYSTEMS; Title Page -- Real-Time Multi-Chip Neural Network for Cognitive Systems; Copyright page; Dedication; Contents; Preface; List of Contributors; List of Figures; List of Tables; List of Abbreviations; Chapter 1 -- Introduction; 1.1 A Real-Time Reconfigurable Multi-Chip Architecture for Large-Scale Biophysically Accurate Neuron Simulation; 1.2 The Inferior Olivary Nucleus Cell; 1.2.1 Abstract Model Description; 1.2.2 The ION Cell Design Configuration; 1.2.3 The ION Cell Cluster Controller; 1.3 Multi-Chip Dataflow Architecture
1.4 Organization of the BookReferences; Chapter 2 -- Multi-Chip Dataflow Architecture for Massive Scale Biophysically Accurate Neuron Simulation; 2.1 Introduction; 2.2 System Design Configuration; 2.2.1 Requirements; 2.2.2 Zero Communication Time: The Optimal Approach; 2.2.3 Localising Communication: How to Speed Up the Common Case; 2.2.4 Network-on-Chips; 2.2.5 Localise Communication between Clusters; 2.2.6 Synchronisation between the Clusters; 2.2.7 Adjustments to the Network to Scale over Multiple FPGAs; 2.2.8 Interfacing the Outside World: Inputs and Outputs
2.2.9 Adding Flexibility: Run-Time Configuration2.2.10 Parameters of the System; 2.2.11 Connectivity and Structure Generation; 2.3 System Implementation; 2.3.1 Exploiting Locality: Clusters; 2.3.2 Connecting Clusters: Routers; 2.3.3 Tracking Time: Iteration Controller; 2.3.4 Inputs and Outputs; 2.3.5 The Control Bus for Run-Time Configuration; 2.3.6 Automatic Structure Generation and Connectivity Generation; 2.4 Experimental Results; 2.5 Conclusions; References; Chapter 3 -- A Real-Time Hybrid Neuron Network for Highly Parallel Cognitive Systems; 3.1 Introduction
3.2 The Calculation Architecture3.2.1 The Physical Cell Overview; 3.2.2 Initialising the Physical Cells; 3.2.3 Axon Hillock + Soma Hardware; Exponent operand schedule; Axon hillock and soma compartment controller; 3.2.4 Dendrite Hardware; Dendrite network operation; Dendrite combine operation; Dendrite compartmental latency; 3.2.5 Calculation Architecture Latency; 3.2.6 Exponent Architecture; 3.3 The Calculation Architecture; 3.3.1 Communication Architecture Overview; 3.3.2 Cluster Controller; 3.3.3 Routing Network; Routing method Design specification3.3.4 Interface Bridge; 3.4 Experimental Results; 3.4.1 Evaluation Method; Building a test set; Design simulation; SystemC synthesis; Post-synthesis simulation; VHDL implementation; 3.4.2 Evaluation Results; Accuracy results; Latency results; Resource usage; 3.4.3 Model Configuration; 3.5 Conclusions; References; Chapter 4 -- Digital Neuron Cells for Highly Parallel Cognitive Systems; 4.1 Introduction; 4.2 System Design Configuration; 4.2.1 Requirements; 4.2.2 Input and Output; 4.2.3 Parameters
Note 4.2.4 Scalability of Network
Local Note eBooks on EBSCOhost EBSCO eBook Subscription Academic Collection - North America
Subject Neural networks (Computer science)
Genre/Form Electronic books.
Added Author Van Leuken, Rene.
Other Form: Print version: Zjajo, Amir. Real-Time Multi-Chip Neural Network for Cognitive Systems. Aalborg : River Publishers, ©2019
ISBN 8770220336
9788770220330 (electronic bk.)