LEADER 00000cam a2200721La 4500
001 ocm50174882
003 OCoLC
005 20160527041156.1
006 m o d
007 cr cn|||||||||
008 020517s2000 maua ob 001 0 eng d
019 533449304|a606455167|a650011202
020 1580534716|q(electronic book)
020 9781580534710|q(electronic book)
020 |z1580531075|q(alkaline paper)
020 |z9781580531078|q(alkaline paper)
035 (OCoLC)50174882|z(OCoLC)533449304|z(OCoLC)606455167
|z(OCoLC)650011202
040 N$T|beng|epn|cN$T|dOCLCQ|dYDXCP|dOCLCQ|dTUU|dOCLCQ|dTNF
|dOCLCQ|dE7B|dOCLCF|dOCLCE|dOCLCA|dNLGGC|dOCLCO|dOCLCQ
|dOCLCO|dOCL|dOCLCO|dOCLCQ
042 dlr
049 RIDW
050 4 TK7895.E42|bR37 2000eb
072 7 TEC|x008050|2bisacsh
072 7 TEC|x008030|2bisacsh
072 7 COM|x036000|2bisacsh
082 04 621.39/5|221
084 ST 150|2rvk
084 ZN 4904|2rvk
090 TK7895.E42|bR37 2000eb
100 1 Rajsuman, Rochit.|0https://id.loc.gov/authorities/names/
n89658334
245 10 System-on-a-chip :|bdesign and test /|cRochit Rajsuman.
264 1 Boston, MA :|bArtech House,|c2000.
300 1 online resource (xiii, 277 pages) :|billustrations.
336 text|btxt|2rdacontent
337 computer|bc|2rdamedia
338 online resource|bcr|2rdacarrier
340 |gpolychrome|2rdacc
347 text file|2rdaft
490 1 Artech House signal processing library
504 Includes bibliographical references and index.
505 0 Design -- Architecture of the present-day SoC -- Design
issues of SoC -- Hardware-software codesign -- Codesign
flow -- Codesign tools -- Core libraries, EDA tools, and
web pointers -- Core libraries -- EDA tools and vendors --
Web pointers -- Design methodology for logic cores -- SoC
design flow -- General guidelines for design reuse --
Synchronous design -- Memory of mixed-signal design -- On-
chip buses -- Clock distribution -- Clear/set/reset
signals -- Physical design -- Deliverable models -- Design
process for soft and firm cores -- Design flow --
Development process for soft/firm cores -- RTL guidelines
-- Soft/firm cores productization -- Design process for
hard cores -- Unique design issues in hard cores --
Development process for hard cores -- Sign-off checklist
and deliverables -- Sign-off checklist -- Soft core
deliverables -- Hard core deliberables -- System
integration -- Designing with hard cores -- Designing with
soft cores -- System verification -- Design methodology
for memory and analog cores -- Why large embeded memories
-- Design methodology for embedded memories -- Circuit
techniques -- Memory compiler -- Simulation models --
Specifications of analog circuits -- Analog-to-digital
converter -- Phase-locked loops -- High-speech circuits --
Rambus ASIC cell -- IEEE 1394 serial bus (Firewire) PHY
layer -- High-Speed I/O -- Design validation -- Core-level
validation -- Core validation plan -- Testbenches -- Core-
level timing verification -- Core interface verification -
- Protocol verification -- Gate-level simulation -- SoC
design validation -- Cosimulation -- Emulation -- Hardware
prototypes -- Core and SoC design examples --
Microprocessor cores -- V830R/AV superscaler RISC core --
Design of powerPC 603e core -- Comments of memory core
generation -- Core integration and on-chip bus -- Examples
of SoC -- Media processors -- Testbility of set-top box
SoC -- Testing of digital logic cores -- SoC test issues -
- Access, control, and isolation -- IEEE P1500 effort --
Cores without boundary scan -- Core test language -- Core
with boundary scan -- Core test and IP protection -- Test
methodology for design reuse -- Guidelines for core
testability -- High-level test synthesis -- Testing of
microprocessor cores -- Built-in self-test method --
Examples: testability features of ARM processor core --
Debug support for microprocessor cores -- Testing of
embedded memories -- Memory fault models and test
algorithms -- Fault models -- Test algorithms --
Effectiveness of test algorithms -- Modification with
multiple data background -- Modification for multiport
memories -- Algorithm for double-buffered memories -- Test
methods for embedded memories -- Testing through ASIC
functional test -- Test application by direct access --
Test application by scan or collar register -- Memory
built-in self-test -- Testing by on-chip microprocessor --
Summary of test methods for embedded memories -- Memory
redundancy and repair -- Hard repair -- soft repair --
mError detection and correction codes -- Production
testing of SoC with large embedded memory -- Testing of
analog and mixed-signal cores -- Analog parameters and
characterization -- Digital-to-analog converter -- Analog-
to-digital converter -- Phase-locked loop -- Design-for-
test and buil-in self-test methods for analog cores --
Fluence technology's analog BIST -- LogiVision's analog
BIST -- Testing by on-chip microprocessor -- IEEE P1149.4
-- Testing of specific analog circuits -- Rambus ASIC cell
-- Teting of 1394 serial bus/firewire -- Iddq testing --
Physical defects -- Bridging (shorts) -- Gate-oxide
defects -- Open (breaks) -- Effectiveness of iddq testing
-- Iddq testing difficulties in SoC -- Design-for-iddq-
testing -- Iddq test vector generation -- Production
testing -- Production test flow -- At-speed testing -- RTD
and dead cycles -- Fly-by -- Speed binning -- Production
throughput and materials handling -- Test logistics --
Tester setup -- Multi-DUT testing.
506 |3Use copy|fRestrictions unspecified|2star|5MiAaHDL
533 Electronic reproduction.|b[S.l.] :|cHathiTrust Digital
Library,|d2010.|5MiAaHDL
538 Master and use copy. Digital master created according to
Benchmark for Faithful Digital Reproductions of Monographs
and Serials, Version 1. Digital Library Federation,
December 2002.|uhttp://purl.oclc.org/DLF/benchrepro0212
|5MiAaHDL
583 1 digitized|c2010|hHathiTrust Digital Library|lcommitted to
preserve|2pda|5MiAaHDL
588 0 Print version record.
590 eBooks on EBSCOhost|bEBSCO eBook Subscription Academic
Collection - North America
650 0 Embedded computer systems|xDesign and construction.|0https
://id.loc.gov/authorities/subjects/sh2008119360
650 0 Embedded computer systems|0https://id.loc.gov/authorities/
subjects/sh87006632|xTesting.|0https://id.loc.gov/
authorities/subjects/sh99005648
650 0 Application-specific integrated circuits|xDesign and
construction.|0https://id.loc.gov/authorities/subjects/
sh2009115143
650 7 Embedded computer systems|xDesign and construction.|2fast
|0https://id.worldcat.org/fast/908300
650 7 Embedded computer systems|xTesting.|2fast|0https://
id.worldcat.org/fast/908304
650 7 Embedded computer systems.|2fast|0https://id.worldcat.org/
fast/908298
650 7 Application-specific integrated circuits|xDesign and
construction.|2fast|0https://id.worldcat.org/fast/811723
655 4 Electronic books.
776 08 |iPrint version:|aRajsuman, Rochit.|tSystem-on-a-chip.
|dBoston, MA : Artech House, 2000|z1580531075|w(DLC)
00030613
830 0 Artech House signal processing library.|0https://
id.loc.gov/authorities/names/n97026952
856 40 |uhttps://rider.idm.oclc.org/login?url=http://
search.ebscohost.com/login.aspx?direct=true&scope=site&
db=nlebk&AN=67446|zOnline eBook. Access restricted to
current Rider University students, faculty, and staff.
856 42 |3Instructions for reading/downloading this eBook|uhttp://
guides.rider.edu/ebooks/ebsco
901 MARCIVE 20231220
948 |d20160615|cEBSCO|tebscoebooksacademic|lridw
994 92|bRID
