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008 191026t20192019xx o 000 0 eng d
020 1785617117
020 9781785617119|q(electronic book)
020 |z9781785617102
020 |z1785617109
035 (OCoLC)1125111700
040 EBLCP|beng|epn|cEBLCP|dSTF|dOCLCO|dRB#|dUIU|dOCLCF|dUKAHL
|dNJT|dCUS|dOCLCQ|dVLB|dOCL|dOCLCO|dN$T|dVRC|dOCLCO
049 RIDW
050 4 TK5102.92|b.V575 2019
082 04 621.388|223
090 TK5102.92|b.V575 2019
245 00 VLSI Architectures for Future Video Coding /|cedited by
Maurizio Martina.
264 1 Stevenage :|bInstitution of Engineering & Technology,
|c2019.
264 4 |c©2019
300 1 online resource (385 pages).
336 text|btxt|2rdacontent
337 computer|bc|2rdamedia
338 online resource|bcr|2rdacarrier
347 text file|2rdaft
490 1 IET Materials, circuits and devices series ;|v53
505 0 Intro; Contents; Preface; 1. Scalable transform
architectures for video coding / Sonda Ben Jdidia, Maher
Jridi, Pramod Kumar Meher, Nouri Masmoudi and Ayman Al
Falou; 1.1 Introduction; 1.2 Review of scalable transforms
in HEVC; 1.2.1 Transform coding in HEVC; 1.2.2 Approximate
DCT algorithms and their hardware architecture for HEVC;
1.2.3 Complexity analysis; 1.2.4 Synthesis results; 1.3
Video-coding concept in VVC standard; 1.3.1 VVC encoder
scheme; 1.3.2 Transform coding for VVC standard; 1.3.3
Statistical analysis; 1.4 Approximation for DCT-II
transform and its hardware architecture
505 8 1.4.1 Algorithm description;1.4.2 Approximate 8-point
transform architecture; 1.4.3 Reconfigurable designs for
1D/2D DCT computing; 1.4.4 Video-coding performance; 1.5
New approximation for DST-VII transform; 1.5.1 Algorithm
description; 1.5.2 Video-coding performance; 1.6
Conclusion; References; 2. Joint algorithm-architecture
design of video coding modules / Claudio M. Diniz, Brunno
Abreu, Mateus Grellert, Felipe Martin Sampaio, Daniel
Palomino, Fabio Luıs Livi Ramos, Bruno Zatt and Sergio
Bampi; 2.1 Introduction; 2.2 Video coding evolution and
state of the art
505 8 2.2.1 Evolution of video coding standards; 2.2.2 Overview
of HEVC and VVC codecs; 2.3 Video coding application
analysis; Analysis of VVC and HEVC encoders; 2.4 Rate-
distortion optimization; 2.4.1 Block-partitioning
decisions; 2.4.2 Distortion metrics; 2.4.3 Challenges on
rate-distortion optimization for VVC encoder; 2.5 Inter-
frame prediction; 2.5.1 Integer motion estimation; 2.5.2
Fractional motion estimation; 2.5.3 Dedicated memories for
motion estimation; 2.6 Intra-frame prediction; 2.6.1 Intra
-prediction mode decision in H.265/HEVC; 2.6.2 Hardware
architecture for the HEVC intra-prediction
505 8 2.6.3 Challenges on intra-frame prediction architecture
design for VVC encoder2.7 Transforms; 2.7.1 Challenges of
transforms architecture design for VVC encoder; 2.8 In-
loop filter; 2.9 Entropy coding; 2.9.1 Upcoming challenges
related to entropy encoding; 2.10 Conclusions;
Acknowledgements; References; 3. High-throughput
architectures for high-resolution video coding: system
architecture analysis / Grzegorz Pastuszak; 3.1 Hardware
vs. software encoders; 3.2 Hardware optimization
techniques; 3.3 Timing constraints on pixel units; 3.4
Mode decision tradeoffs; 3.4.1 Reconstruction loop
505 8 3.4.2 Transforms; 3.4.3 Mode preselection; 3.4.4 Cost
estimation; 3.5 Motion estimation and compensation; 3.5.1
Search strategy; 3.5.2 Fractional-pel motion estimation;
3.5.3 Access to memories; 3.5.4 Motion vector prediction;
3.6 Entropy coding; 3.7 Summary; References; 4. High-
throughput architectures for high-resolution video coding:
hardwired oriented algorithms and VLSI architectures /
Grzegorz Pastuszak; 4.1 Reconstruction loop; 4.1.1
Transform architectures; 4.1.2 Parallel loops; 4.1.3
Interleaved processing order; 4.2 Rate-distortion
optimization; 4.2.1 RDO based on signal features
505 8 4.2.2 Simplified rate estimation
520 This book examines future video coding from the
perspective of hardware implementation and architecture
design. The book identifies challenges in deploying VLSI
architectures for video coding and postulates potential
solutions with reference to recent research.
588 0 Print version record.
590 eBooks on EBSCOhost|bEBSCO eBook Subscription Academic
Collection - North America
650 0 Digital video.|0https://id.loc.gov/authorities/subjects/
sh94007636
650 0 Coding theory.|0https://id.loc.gov/authorities/subjects/
sh85027654
650 0 Integrated circuits|xVery large scale integration.|0https:
//id.loc.gov/authorities/subjects/sh85067125
650 0 Video compression.|0https://id.loc.gov/authorities/
subjects/sh93007921
650 7 Digital video.|2fast|0https://id.worldcat.org/fast/893738
650 7 Coding theory.|2fast|0https://id.worldcat.org/fast/866237
650 7 Integrated circuits|xVery large scale integration.|2fast
|0https://id.worldcat.org/fast/975602
650 7 Video compression.|2fast|0https://id.worldcat.org/fast/
1166400
655 4 Electronic books.
700 1 Martina, Maurizio,|d1975-|0https://id.loc.gov/authorities/
names/no2020003989|eeditor.
776 08 |iPrint version:|aMartina, Maurizio.|tVLSI Architectures
for Future Video Coding.|dStevenage : Institution of
Engineering & Technology, ©2019|z9781785617102
830 0 Materials, circuits and devices series ;|0https://
id.loc.gov/authorities/names/no2016019132|v53.
856 40 |uhttps://rider.idm.oclc.org/login?url=https://
search.ebscohost.com/login.aspx?direct=true&scope=site&
db=nlebk&AN=2255774|zOnline ebook via EBSCO. Access
restricted to current Rider University students, faculty,
and staff.
856 42 |3Instructions for reading/downloading the EBSCO version
of this ebook|uhttp://guides.rider.edu/ebooks/ebsco
901 MARCIVE 20231220
948 |d20210708|cEBSCO|tEBSCOebooksacademic NEW 5016 |lridw
994 92|bRID
